To improve the generality of synthesis methods of reversible sequential logic circuits and circuit performance indicators, an optimized design of reversible serial shift register is presented based on master-slave D flip-flop, which constructs serial shift registers by cascading and reusing the clock signal and garbage bits. And on this basis， the objective function is constructed and transformed to build modules with shift control and design the n bit reversible register realizing the function of bidirectional serial-in parallel-out and serial-out parallel-out. The results show that the proposed reversible serial shift register has better performances and the method has preferable generality in synthesizing bidirectional registers.