Parasitic inductance has larger influence on Silicon Carbide devices with the increase of switching frequency. This limits full utilization of performance advantages of low switching losses in high frequency applications. By combining theoretical analysis with experimental parametric study, a mathematic model considering parasitic inductance is developed for the basic switching circuit of SiC MOSFET. Main factors which affect the switching characteristics are explored. Moreover, a fast-switching double-pulse test platform is built to measure individual influence of each parasitic inductance on switching characteristics and guidelines are revealed through experimental results. Due to limits of practical layout in high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method of parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of parasitic inductance, which provide guidelines for layout design considerations for SiC-based high-speed switching circuits.